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  • 三電平逆變器共模電壓分析與抑制
    中國測試高 芳, 高 銳
    摘  要:為抑制三電平逆變器共模電壓,以二極管鉗位式拓撲為例,分析其共模電壓產(chǎn)生機理并提出一種抑制共模電壓的簡化三電平5段式空間矢量脈寬調(diào)制算法。該算法通過選取輸出共模電壓幅值小的基本電壓矢量參與調(diào)制來抑制共模電壓。仿真和實驗結果表明,所提算法將共模電壓最大幅值抑制到Vdc/6,比傳統(tǒng)一般算法、抑制共模電壓的7段式、7段式算法分別減少2/3,1/2,0,且可以克服上述3種算法輸出共模電壓幅值隨其調(diào)制度變化而變化的缺點。
    關鍵詞:二極管鉗位式三電平逆變器;空間矢量脈寬調(diào)制;共模電壓;5段式算法
    文獻標志碼:A     文章編號:1674-5124(2015)12-0106-05
    Common-mode voltage analysis and reduction for three-level inverter
    GAO Fang, GAO Rui
    (College of Engineering and Technology,Changchun Vocational Institute of Technology,Jilin 130033,China)
    Abstract: In order to reduce common-mode voltage of three-level inverter, this paper takes diode-clamped topology for instance, analyzes its common-mode voltage generation mechanism and proposes a simplified common-mode voltage reduction three-level five-segment space vector pulse width modulation algorithm(SVPWM). To reduce common-mode voltage, this algorithm selects proper basic voltage vectors to modulate. Simulative and experimental results show that, the proposed algorithm can suppress the maximum value of common-mode voltage to one sixth of DC voltage source value, and decrease respectively about two thirds, one second, zero comparing with traditional space vector modulation, seven-segment, five-segment algorithm. Meanwhile, it can overcome the disadvantage of common-mode voltage value varies with the modulation index of above three algorithms. 
    Keywords: diode-clamped three-level inverter; SVPWM; common-mode voltage; five-segment algorithm
     
     
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